Applications for flat panel displays (active matrix, passive matrix, EL, . . . ) are growing. For example, active matrix flat panel displays can provide advantages over conventional LCD's in the areas of viewing angle, response time and information content. Military and commercial applications such as cockpit displays, mapping displays and imaging systems can utilize these features of flat panel displays to create extremely accurate image reproductions.
A new generation of complex display driver integrated circuits are required to implement flat panel display systems. For instance, there is a need for "next generation" display driver IC's which can take full advantage of the capabilities of current and upcoming flat panel displays by providing extreme image accuracy. Such image accuracy is obtained at the expense of space. Space is a primary concern in applications using flat panel displays because the display driver IC's will have thousands of connections between the display driver IC outputs and the associated flat panel display due to the large number of display driver IC's.
Current system architectures for LCD display drivers for example, employ both row and column display driver IC's. These display driver IC's are high speed circuits having responsibility for accurate generation of large numbers of voltage levels used to drive flat panel displays. These display driver IC's need to be fast, handle large voltages, have a multitude of outputs, provide low offset error, contain tens of thousands of transistors, and yet minimize power. These conflicting design issues require careful analysis in the light of current IC technology.
In prior art flat panel display systems, verification of display driver IC output connectivity required an additional integrated circuit in the display system to sample the outputs of the display driver IC's to be tested, a test point or "bed-of-nails" approach that probed the display driver IC outputs and looked for the proper signal waveform, or a visual inspection of the flat panel display while a test pattern was being implemented. Such verification techniques are time consuming and prone to error.
The output connections for display driver IC's are extremely fine-pitch and are a significant manufacturing and test problem for flat panel display system manufacturers. The present invention provides a solution to this problem by allowing the display connections to the display driver IC's to be tested without human interaction or visual inspection, as previously required.